The present invention relates to an interconnection structure for semiconductor circuits, and more particularly to the interconnection of Very Large Scale Integrated (VLSI) semiconductor circuits having multilayer interconnection construction and which are connected through plugs formed in a connection hole, or "via."
Aluminum films and aluminum alloy films of low resistivity are widely used as the interconnection for semiconductor devices. The density of devices in modem VLSI circuits requires the use of multiple levels of interconnects separated by insulating material. Via holes in the insulating material are used to form plugs which connect these different levels. For dense patterns in the interconnect levels, it is important for the metal layer to be planar.
The planarity requirements require the use of high-aspect ratio vias to connect different interconnection levels. The high aspect ratio requires the vias to be filled with tungsten (W) deposited by chemical vapor deposition (CVD) to form a connection plug. The presence of these W plugs introduces a significant reliability risk due to electromigration when there is a repeated unidirectional current flow between metal levels through the W plug.
Electromigration is the current-assisted flow of atoms of the conductor. The rate of electromigration depends on the current density, ambient temperature, atomic weight of the elements constituting the conductor, the rate of diffusion and the hydrostatic stress present in the conductor. Failure of the circuit can occur when enough mass of the conductor has moved from a location to form a void leading to an open circuit or unacceptable increase in resistance. Alternatively, failure can also occur when conductor atoms collect at a particular site to form hillocks leading to short circuits between parallel conductors or over- or underlying interconnection levels.
In a VLSI circuit where repeated current flow in one direction between two levels of Al interconnections connected by a W plug can occur frequently, the interface between W plugs and Al interconnections are potential sites for electromigration failure. This is because tungsten does not electromigrate under conditions present during operation of the VLSI circuit due to its large atomic weight. Consequently, a flux divergence is introduced at the tungsten plug/Aluminum interface. This results in movement of Al atoms away from the plug when the electron flow direction is away from the plug. Voiding can therefore result at the plug-Aluminum interface, leading to open circuits.
This problem can be greatly exacerbated by the existence of poor mechanical adhesion between the base of the plug and underlying interconnect. Poor adhesion can result from the presence of etch residue from the via etch process. Poor mechanical adhesion is impossible to detect by conventional electrical testing due to inadequate sensitivity of the in-fab electrical test systems. However, in poorly adherent W plugs, very little Al removal is required to separate the W plug from the interconnect under unidirectional current flow. Therefore a very small void can lead to an unacceptably large increase in circuit resistance.